The invention relates generally to etching of silicon integrated circuits. In particular, the invention relates to etching silicon oxide and related materials in a process that is capable of greatly reduced etching rates for silicon nitride and other non-oxide materials but still produces a vertical profile in the oxide.
In the fabrication of silicon integrated circuits, the continuing increase in the number of devices on a chip and the accompanying decrease in the minimum feature sizes have placed increasingly difficult demands upon many of the many fabrication steps used in their fabrication including depositing layers of different materials onto sometimes difficult topologies and etching further features within those layers.
Oxide etching has presented some of the most difficult challenges. Oxide is a somewhat generic term used for silica, particularly silicon dioxide (SiO2) although slightly non-stoichiometric compositions SiOx are also included, as is well known. The term oxide also covers closely related materials, such as oxide glasses including borophosphosilicate glass (BPSG) and other silicate glasses. Some forms of silicon oxynitride are considered to more closely resemble an oxide than a nitride. Small fractions of dopants such as fluorine or carbon may be added to the silica to reduce its dielectric constant. Oxide materials are principally used for electrically insulating layers, often between different levels of the integrated circuit. Because of the limits set by dielectric breakdown, the thickness of the oxide layers cannot be reduced to much below 0.5 to 1 xcexcm. However, the minimum feature sizes of contact and via holes penetrating the oxide layer are being pushed to well below 0.5 xcexcm, the current developmental goal being 0.13 xcexcm. The result is that the holes etched in the oxide must be highly anisotropic and must have high aspect ratios, defined as the depth to the minimum width of a hole. A further problem arises from the fact that the underlying silicon may be formed with active doped regions of thicknesses substantially less than the depth of the etched hole (the oxide thickness). Due to manufacturing variables, it has become impossible to precisely time a non-selective oxide etch to completely etch through the silicon oxide without a substantial probability of also etching through the underlying active silicon region.
Anisotropic via profiles can obtained by dry plasma etching in which an etching gas, usually a fluorine-based gas, is electrically excited into a plasma. The plasma conditions may be adjusted to produce highly anisotropic etching in many materials. However, the anisotropy should not be achieved by operating the plasma reactor in a purely sputtering mode in which the plasma ejects particles toward the wafer with sufficiently high energy that they sputter the oxide. Sputtering is generally non-selective. High-energy sputtering also seriously degrades semiconducting silicon exposed at the bottom of the etched contact hole. If is metal is exposed at the bottom of a via, sputtering tends to sputter some metal onto the sidewalls of the via, vitiating the effect of subsequently deposited barrier layers.
In view of these and other problems, selective etching processes have been developed which depend more upon chemical effects. These processes are often described as reactive ion etching (RIE). The most popular active etching gas is a fluorocarbon (including hydrofluorocarbons) although some effort is being expended with other fluorinated gases such as SF6. A sufficiently high degree of selectivity allows new structures to be fabricated without the need for precise lithography for each level.
An example of such an advanced structure is a self-aligned contact (SAC), illustrated in the cross-sectional view of FIG. 1. The illustrated SAC structure includes parts of two transistors formed on a silicon substrate 2. A polysilicon gate layer 4, a tungsten silicide barrier and glue layer 6, and a silicon nitride cap layer 8 are deposited and photolithographically formed into two closely spaced gate structures 10 having a gap 12 therebetween. Chemical vapor deposition (CVD) then deposits onto the wafer a substantially conformal layer 14 of silicon nitride (Si3N4), which coats the top and sides of the gate structures 10 as well as a bottom 15 of the gap 12. In practice, the nitride deviates from the indicated stoichiometry and may have a composition of SiNx, where x is between 1 and 1.5; the nitride acts as an electrical insulator. Dopant ions are ion implanted using the gate structures 10 as a mask to form a self-aligned p-type or n-type well 16, which acts as a common source for the two transistors having respective gates 10. The drain structures of the two transistors are not illustrated.
An oxide field layer 18 is deposited over this previously defined structure, and an organic photoresist layer 20 is deposited over the oxide layer 18 and photographically defined into a mask. A subsequent oxide etching step etches a contact hole 22 through the oxide layer 18 and stops on a portion 24 of the nitride layer 14 underlying the hole 22. It is called a contact hole because the metal subsequently deposited into the contact hole 22 forms a contact to underlying silicon rather than to a metallic interconnect layer. If an underlying metallic interconnect is contacted, the structure is called a via hole and is included within some aspects of the present invention. Unless specifically stated otherwise, references to contacts apply equally well to vias. A soft post-etch plasma treatment with hydrogen or nitrogen removes the nitride portion 24 at the bottom 15 of the gap 12. The silicon nitride acts as an electrical insulator between the gate structure 10 and the metal, usually aluminum, thereafter filled into the contact hole 22.
Because the nitride acts as an insulator, the SAC structure and process offer the advantage that the contact hole 22 may be wider than the width of the gap 12 between the gate structures 10. In advanced devices, the gap 12 between the gate structures 10 may be very small, less than 10 nm, while the width of the contact hole 22 may be significantly larger. Additionally, the photolithographic registry of the contact hole 22 with the gate structures 10 need not be precise. The imprecise definition of the mask in the photoresist layer 20 may place one side of the contact hole 22 near the middle of the gap 12, as illustrated in FIG. 2, with a narrow side gap 26 forming at the bottom of the contact hole 22 on the side of one of the gate structures. The width of the side gap 26 may be 0.1 xcexcm or less. Nonetheless, this may still provide a good contact. However, to achieve these beneficial effects, the SAC oxide etch must be highly selective to nitride. That is, the process must produce an oxide etch rate that is much greater than the nitride etch rate. Numerical values of selectivity are calculated as the ratio of the oxide to nitride etch rates. Selectivity is especially critical at corners 28 of the nitride layer 14 above and next to the gap 12 or 26 since the nitride corners 28 are the portion of the nitride exposed the longest to the oxide etch. Furthermore, they have a geometry favorable to fast etching that tends to create facets at the nitride corners 28. The corners of the gate structures 10 will thereby be prematurely exposed if the faceting is severe enough.
Furthermore, increased selectivity is being required with the increased usage of chemical mechanical polishing (CMP) for planarization of an oxide layer over a curly wafer. The polishing planarization produces a flat top surface in the oxide layer over the wavy underlying substrate, thereby producing an oxide layer of significantly varying thickness. To compensate for this variable thickness, the time of the oxide etch must be set significantly higher, for example, by 100% than the etching time for the design thickness to assure penetration of the variable thickness oxide. This extra etching time, called over etch, also accommodates other process variations. However, for the regions with a thinner oxide, the nitride is exposed that much longer to the etching environment.
Ultimately, the required degree of selectivity is reflected in the reduced probability of an electrical short through the nitride layer 14 between the gate structures 10 and the metal filled into the contact hole 22. The etch must also be selective to photoresist, for example, at facets 29 that develop at corners of the mask 20, but the requirement of photoresist selectivity is often not so stringent since the photoresist layer 20 may be made much thicker than the nitride layer 14. However, for very advanced devices requiring lithographic resolution of 0.18 and lower, the photoresist thickness is limited so photoresist selectivity may become critical.
In the future, the most demanding etching steps are projected to be performed in high-density plasma (HDP) etch reactors. Such HDP etch reactors achieve a high-density plasma having a minimum average ion density of 1011 cmxe2x88x923 across the plasma exclusive of the plasma sheath. Although several techniques are available for achieving a high-density plasma such as electron cyclotron resonance and remote plasma sources, the commercially most important techniques involve inductively coupling RF energy into the source region. The inductive coil may be cylindrically wrapped around the sides of chamber or be a flat coil above the top of the chamber or represent some intermediate or combination geometry or other variants.
An example of an inductively coupled plasma etch reactor is the Inductive Plasma Source (IPS) etch reactor, which is available from Applied Materials and which Collins et al. describe in U.S. patent application Ser. No. 08/733,544, filed Oct. 21, 1996 and in European Patent Publication EP-840,365-A2. As shown in FIG. 3, a wafer 30 to be processed is closely supported on a cathode pedestal 32 supplied with RF power from a first RF power supply 34. A silicon ring 36 surrounds the pedestal 32 and is controllably heated by an array of heater lamps 38. A grounded silicon wall 40 surrounds the plasma processing area. A silicon roof 42 overlies the plasma processing area, and lamps 44 and water cooling channels 46 control its temperature. In the described embodiments, the silicon roof 42 is grounded, but it may be separately RF biased for other applications. The volume of the vacuum processing chamber is about 23 liters for a 200 mm wafer. Chamber volumes scale between the second and third power of the wafer diameter. The temperature-controlled silicon ring 36 and silicon roof 42 may be used to scavenge fluorine from the fluorocarbon plasma. For some applications, fluorine scavenging can be accomplished by a solid carbon body, such as amorphous or graphitic carbon, or by other non-oxide silicon-based or carbon-based materials, such as silicon carbide.
Processing gas is supplied from one or more bottom gas feeds 48 through a bank of mass flow controllers 50 under the control of a system controller 52, in which is stored the process recipe in magnetic or semiconductor memory. Gas is supplied from respective gas sources 54, 56. The conventional oxide etch recipe uses a combination of a fluorocarbon or hydrofluorocarbon and argon. Octafluorocyclobutane (C4F8) and trifluoromethane (CHF3) are popular fluorocarbons, but other hydrogen-free fluorocarbons, hydrofluorocarbons, and combinations thereof are used. The etching gas composition is the subject of at least part of this invention.
A metal manifold wall 58 connected mechanically and electrically to the silicon chamber wall 40 defines a pumping channel 59 surrounding the lower portion the main processing area and connected to it by an annular constricted orifice 60. An unillustrated robot blade transfers the wafer 30 into and out of the chamber through an unillustrated slit valve associated with an opening 61 in the manifold wall 58. An unillustrated vacuum pumping system connected to the a pumping channel 59 maintains the chamber at a preselected pressure, as set by the controller 52.
The controller 52 controls the various reactor element according to the etch recipe and thus determines the etch process.
In the used configuration, the silicon roof 42 is grounded, but its semiconductor resistivity and thickness are chosen to pass generally axial RF magnetic fields produced by an inner inductive coil stack 62 and an outer inductive coil stack 64 positioned above the roof 42 and powered by respective RF power supplies 66, 68. A single RF power supply and an RF power splitter may be substituted. In the IPS reactor used in the experiments to be the described, the frequencies of the three RF power supplies were different and all in the low megahertz range.
Optical emission spectroscopy (OES) is a conventional monitoring process used for end-point detection in plasma etching. An optical fiber 70 is placed in a hole 72 penetrating the chamber wall 40 to laterally view the plasma area 74 above the wafer 30. An optical detector system 76 is connected to the other end of the fiber 70 and includes one or more optical filters and processing circuitry that are tuned to the plasma emission spectrum associated with the aluminum, copper, or other species in the plasma. Either the raw detected signals or a trigger signal is electronically supplied to the controller 52, which can use the signals to determine that one step of the etch process has been completed when either a new signal appears or an old one decreases. With this determination, the controller 52 can adjust the process recipe or end the etching step according to the power levels set primarily in the source power supplies 66, 68.
The IPS chamber can be operated to produce a high-density or a low-density plasma. The temperature of the silicon surfaces and of the wafer can be controlled. The bias power applied to the cathode 32 by the bias power supply 34 can be adjusted independently of the source power 66, 68 applied to the coils 62, 64 and can be made small enough or even zero for a soft plasma etch process. Alternatively, it may be left electrically floating, but a negative DC self-bias generally develops nonetheless.
It has become recognized, particularly in the use of HDP etch reactors, that selectivity in an oxide etch can be achieved by a fluorocarbon etching gas forming a polymer layer upon the non-oxide portions, thereby protecting them from etching, while the oxide portions remain exposed to the etching environment because the oxygen included in the oxide combines with the carbon included in any incipiently forming polymer to form volatile CO2. That is, oxide prevents the formation of a protective carbon-based polymer. Also, polymer forming on the oxide sidewalls promotes vertical etching profiles. It is believed that the temperature-controlled silicon ring 36 and roof 42 in the reactor of FIG. 3 control the fluorine content of the polymer and hence its effectiveness against etching by the fluorocarbon plasma when the polymer overlies a non-oxide. However, the polymerization mechanism is responsible for a major problem in oxide etching if high selectivity is being sought. If an excessive amount of polymer is deposited on the oxide or nitride surfaces in the contact hole being etched, the hole can close up and the etching is stopped prior to completion of the etching to the bottom of the hole. This deleterious condition is referred to as etch stop.
The selectivity is partly achieved in many recipes by the use of a chemically inactive diluent gas, most typically argon (Ar). The argon is at least partially ionized in the plasma so that it is accelerated across the plasma sheath adjacent to the wafer 30. The energetic argon, at least at lower energy, promotes the chemically based etching of silica and other oxide layers in a process often referred to as reactive ion etching (RIE). The directionality of the argon ions also promotes the formation of the protective polymer on the sidewalls while acting to prevent its formation on the hole bottom.
As mentioned, argon is the most popular diluent gas. Many references for oxide etching based on fluorine chemistry mention other noble gases including helium, neon, xenon, and krypton (He, Ne, Xe, Kr) as alternatives to argon, but no advantage is ascribed to any of them. See, for example, U.S. Pat. No. 5,173,151 to Namose and U.S. Pat. No. 5,811,357 to Armacost et al. On the other hand, in some types of metal etching based on chlorine chemistry, xenon is preferred. See, for example, U.S. Pat. No. 5,384,009 to Mak et al. Similarly, in some types of silicon etching based on bromine, xenon or krypton is preferred. See, for example, U.S. Pat. No. 4,786,359 to Stark et al.
A further problem with polymerization in a fluorine-based etch is that the polymer formation may depend critically upon the processing conditions. It may be possible to achieve high selectivity with processing conditions produced by one set of processing parameters, but very small variations in those conditions may be enough to either substantially reduce the selectivity on one hand or to produce etch stop on the other. Either result is unacceptable in a commercial process. Such variations can occur in at least two ways. The conditions at the middle of the wafer may vary from those at the center. Furthermore, the conditions may change over time on the order of minutes as the chamber warms up or on the order of days as the equipment ages or as chamber parts are replaced. It is felt that hardware can be controlled to no better than xc2x15% or 6%, and a safety margin or 3 to 6 is desired. Mass flow controllers 46 are difficult to control to less than xc2x11 sccm (standard cubic centimeter per minute) of gas flow so gas flows of any constituent gas of only a few sccm are prone to large percentage variations.
These factors indicate that a commercially viable etch process must have a wide process window. That is, moderate variations in such parameters as gas composition and chamber pressure should produce only minimal changes in the resultant etching.
Although octafluorocyclobutane (C4F8) remains the most popular oxide etching gas for advanced oxide etching, we observe that it suffers from too narrow a process window. Furthermore, although C4F8 is known to provide high selectivity at the bottom of the etching hole, it provides little sidewall passivation, which is required for the desired vertical profiles. Also, C4F8 has a boiling point of +1xc2x0 C., which is considered somewhat high for use as a gaseous etchant, especially in view of a trend to operate with very cold cathodes. Another heavy fluorocarbon that is used for oxide etching is C5F8, typically in the form of one of the isomers of octafluoropentadiene. Often carbon monoxide (CO) is added to C4F8 to increase the sidewall passivation as well as increase general nitride selectivity. However, CO is not only toxic, it also forms carbonyls with nickel and iron in gas cylinders and supply lines. The carbonyls are believed to contaminate wafers. For these reasons, the use of CO is not preferred.
Hung et al. in U.S. Pat. No. 6,387,287, filed Mar. 25, 1999, disclose the advantageous use of the heavy fluorocarbon gas hexafluorobutadiene (C4F6) in combination with argon or possibly other noble gases for etching oxide in the IPS chamber of FIG. 2. This patent application is incorporated herein by reference in its entirety. Hexafluorobutadiene has the chemical structure illustrated in FIG. 4. The combination of C4F6 and large amounts of Ar is shown to produce highly isotropic etching with acceptable selectivity to corner nitride in SAC and related applications. Importantly, the process is shown to exhibit a wide process window.
However, even better nitride selectivity is desired, and even wider process windows are desired. Furthermore, some applications involving a very deep oxide etch do not require such high nitride selectivity but require a high selectivity to photoresist. For example, etching a trench for forming sidewall capacitors for dynamic random access memory (DRAM) may require etching the fairly narrow trench through 1.5 xcexcm or more of oxide while using only a photoresist mask. In this application, trench profile is less an issue than is photoresist selectivity.
Other applications require etching an oxide layer into which holes have already been formed. This geometry requires that the oxide corners not be unduly faceted.
The use of xenon (Xe) as the diluent gas in fluorine-based oxide etching provides very high selectivity to nitride and a wide process window, especially in combination with heavy fluorocarbons, for example, hexafluorobutadiene (C4F6). For nitride selectivity and oxide profile control, the amount of xenon should be approximately equal to or, in some circumstances, substantially greater than that of the fluorocarbon. Krypton (Kr) promises similar effects.
Xenon dilution of a heavy fluorocarbon gas is particularly advantageous in etching an oxide layer in an area encompassing a hole etched into the oxide layer, thereby reducing faceting of the oxide corner.
The combination of Xe and heavy fluorocarbons such as C4F6 is also advantageous in avoiding faceting of oxide corners.
The use of Xe or Kr as a carrier gas for oxide etching can also be extended to other fluorine-containing etching, especially the heavier hydrogen-free fluorocarbons.